Along with development in microfabrication technology, an LSI has been improved in performance by integrating more transistors into a single chip. However, because of limitation of miniaturization or increase of utilization cost of a state-of-the-art process, it is not necessarily an optimum solution to develop such conventional integration into a single chip. Therefore, three-dimensional integration obtained by stacking a plurality of LSIs is a promising technique.
To obtain desired performance in stacked LSIs, a communication function between the stacked LSIs is important. A powerful solution for a communication system for stacked LSIs is multi-pin 3D communication utilizing Through Silicon Vias.
Here, when performing 3D communications utilizing Through Silicon Vias, it is assumed that more than several thousand Through Silicon Vias are formed, and toward mass production it is required to remedy a connection defect or the like of Through Silicon Vias so that yield is improved. Patent Document 1 has referred to having spare Through Silicon Vias for improving yield.    Patent Document 1: Japanese Patent Application Laid-Open Publication No. 2007-158237